Difference between revisions of "FT2232H breakout board"

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Line 92: Line 92:
<tr><td>3</td><td>BDBUS0</td></tr>
<tr><td>3</td><td>BDBUS0</td></tr>
<tr><td>4</td><td>BDBUS1</td></tr>
<tr><td>4</td><td>BDBUS1</td></tr>
<tr><td>5</td><td>BDBUS2</td></tr>
<tr><td>6</td><td>BDBUS3</td></tr>
<tr><td>7</td><td>BDBUS4</td></tr>
<tr><td>8</td><td>BDBUS5</td></tr>
<tr><td>9</td><td>BDBUS6</td></tr>
<tr><td>10</td><td>BDBUS7</td></tr>
<tr><td>11</td><td>BCBUS0</td></tr>
<tr><td>12</td><td>BCBUS1</td></tr>
<tr><td>13</td><td>BCBUS2</td></tr>
<tr><td>14</td><td>BCBUS3</td></tr>
<tr><td>15</td><td>BCBUS4</td></tr>
<tr><td>16</td><td>BCBUS5</td></tr>
<tr><td>17</td><td>BCBUS6</td></tr>
<tr><td>18</td><td>BCBUS7</td></tr>
<tr><td>19</td><td>3V3</td></tr>
<tr><td>20</td><td>3V3</td></tr>
</table>


<table border=1>
<tr><td>GND</td><td>1</td><td>2</td><td>GND</td></tr>
<tr><td>BDBUS0</td><td>3</td><td>4</td><td>BDBUS1</td></tr>
<tr><td>5</td><td>BDBUS2</td></tr>
<tr><td>5</td><td>BDBUS2</td></tr>
<tr><td>6</td><td>BDBUS3</td></tr>
<tr><td>6</td><td>BDBUS3</td></tr>

Revision as of 17:16, 11 May 2012

FT2232H breakout board

This is the documentation page for the FT2232H breakout board.

overview

The FT2232H breakout board has an USB connector, two 20-pin HDR-standard IO connectors (one for BUS0 and one for BUS1), and one 40-pin terasic compatible connector. The brains of the PCB, of course, is an FT2232H chip.

External resources

pinout

The SV1 connector is designed to be connected to the 40 pin expansion connector of Terasic FPGA boards. This can be done with a standard 40 pin IDE cable, provided that it isn't too long.

40-pin connector SV1 is connected as follows:

1ACBUS5
2NC
3NC
4NC
5ADBUS0
6ADBUS1
7ADBUS2
8ADBUS3
9ADBUS4
10ADBUS5
115V
12GND
13ADBUS6
14ADBUS7
15ACBUS0
16ACBUS1
17ACBUS2
18ACBUS3
19ACBUS4
20ACBUS5
21ACBUS6
22ACBUS7
23BDBUS0
24BDBUS1
25BDBUS2
26BDBUS3
27BDBUS4
28BDBUS5
293V3
30GND
31BDBUS6
32BDBUS7
33BCBUS0
34BCBUS1
35BCBUS2
36BCBUS3
37BCBUS4
38BCBUS5
39BCBUS6
40BCBUS7

Connectors SV4 and SV5 are designed to be compatible with the 20-pin IO connectors also found on other BitWizard boards.

20-pin connector SV4 is connected as follows:

1GND
2GND
3ADBUS0
4ADBUS1
5ADBUS2
6ADBUS3
7ADBUS4
8ADBUS5
9ADBUS6
10ADBUS7
11ACBUS0
12ACBUS1
13ACBUS2
14ACBUS3
15ACBUS4
16ACBUS5
17ACBUS6
18ACBUS7
193V3
203V3

20-pin connector SV5 is connected as follows:

1GND
2GND
3BDBUS0
4BDBUS1
5BDBUS2
6BDBUS3
7BDBUS4
8BDBUS5
9BDBUS6
10BDBUS7
11BCBUS0
12BCBUS1
13BCBUS2
14BCBUS3
15BCBUS4
16BCBUS5
17BCBUS6
18BCBUS7
193V3
203V3


GND12GND
BDBUS034BDBUS1
5BDBUS2
6BDBUS3
7BDBUS4
8BDBUS5
9BDBUS6
10BDBUS7
11BCBUS0
12BCBUS1
13BCBUS2
14BCBUS3
15BCBUS4
16BCBUS5
17BCBUS6
18BCBUS7
193V3
203V3
  • led1 is connected to VCC

Jumper settings

For 2.0

SV2: 3V3 supply selection
1-2: Direct from FPGA board (through 40-pin connector)
2-3: From regulator (see SV3 settings)

SV3: Regulator power source selection
1-2: Powered from USB
2-3: Powered from FPGA board (through 40-pin connector)

For 2.1

J1: 3V3 supply selection
1-2: Direct from FPGA board (through 40-pin connector)
2-3: From regulator (see SV3 settings)

J2: Regulator power source selection (physical position is the same as in 2.0, only numbering has changed)
1-2: Powered from FPGA board (through 40-pin connector)
2-3: Powered from USB

future hardware enhancements

Changelog

2.1

  • Renamed SV2 to J1
  • Renamed SV3 to J2
  • Jumper settings marked on PCB
  • Moved center of mounting holes to 3mm from PCB edge

2.0

  • Initial public release