Difference between revisions of "FT2232H breakout board"
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== Jumper settings == |
== Jumper settings == |
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==== For 2.0 ==== |
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SV2: 3V3 supply selection<br> |
SV2: 3V3 supply selection<br> |
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1-2: Powered from USB<br> |
1-2: Powered from USB<br> |
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2-3: Powered from FPGA board (through 40-pin connector)<br> |
2-3: Powered from FPGA board (through 40-pin connector)<br> |
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==== For 2.1 ==== |
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J1: 3V3 supply selection<br> |
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1-2: Direct from FPGA board (through 40-pin connector)<br> |
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2-3: From regulator (see SV3 settings)<br> |
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J2: Regulator power source selection<br> (physical position is the same as in 2.0, only numbering has changed) |
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1-2: Powered from FPGA board (through 40-pin connector)<br> |
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2-3: Powered from USB<br> |
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== future hardware enhancements == |
== future hardware enhancements == |
||
Revision as of 15:03, 25 November 2011
FT2232H breakout board
This is the documentation page for the FT2232H breakout board.
overview
The FT2232H breakout board has an USB connector, two 20-pin HDR-standard IO connectors (one for BUS0 and one for BUS1), and one 40-pin terasic compatible connector. The brains of the PCB, of course, is an FT2232H chip.
External pages
pinout
40-pin connector SV1 is connected as follows:
| 1 | ACBUS5 |
| 2 | NC |
| 3 | NC |
| 4 | NC |
| 5 | ADBUS0 |
| 6 | ADBUS1 |
| 7 | ADBUS2 |
| 8 | ADBUS3 |
| 9 | ADBUS4 |
| 10 | ADBUS5 |
| 11 | 5V |
| 12 | GND |
| 13 | ADBUS6 |
| 14 | ADBUS7 |
| 15 | ACBUS0 |
| 16 | ACBUS1 |
| 17 | ACBUS2 |
| 18 | ACBUS3 |
| 19 | ACBUS4 |
| 20 | ACBUS5 |
| 21 | ACBUS6 |
| 22 | ACBUS7 |
| 23 | BDBUS0 |
| 24 | BDBUS1 |
| 25 | BDBUS2 |
| 26 | BDBUS3 |
| 27 | BDBUS4 |
| 28 | BDBUS5 |
| 29 | 3V3 |
| 30 | GND |
| 31 | BDBUS6 |
| 32 | BDBUS7 |
| 33 | BCBUS0 |
| 34 | BCBUS1 |
| 35 | BCBUS2 |
| 36 | BCBUS3 |
| 37 | BCBUS4 |
| 38 | BCBUS5 |
| 39 | BCBUS6 |
| 40 | BCBUS7 |
20-pin connector SV4 is connected as follows:
| 1 | GND |
| 2 | GND |
| 3 | ADBUS0 |
| 4 | ADBUS1 |
| 5 | ADBUS2 |
| 6 | ADBUS3 |
| 7 | ADBUS4 |
| 8 | ADBUS5 |
| 9 | ADBUS6 |
| 10 | ADBUS7 |
| 11 | ACBUS0 |
| 12 | ACBUS1 |
| 13 | ACBUS2 |
| 14 | ACBUS3 |
| 15 | ACBUS4 |
| 16 | ACBUS5 |
| 17 | ACBUS6 |
| 18 | ACBUS7 |
| 19 | 3V3 |
| 20 | 3V3 |
20-pin connector SV5 is connected as follows:
| 1 | GND |
| 2 | GND |
| 3 | BDBUS0 |
| 4 | BDBUS1 |
| 5 | BDBUS2 |
| 6 | BDBUS3 |
| 7 | BDBUS4 |
| 8 | BDBUS5 |
| 9 | BDBUS6 |
| 10 | BDBUS7 |
| 11 | BCBUS0 |
| 12 | BCBUS1 |
| 13 | BCBUS2 |
| 14 | BCBUS3 |
| 15 | BCBUS4 |
| 16 | BCBUS5 |
| 17 | BCBUS6 |
| 18 | BCBUS7 |
| 19 | 3V3 |
| 20 | 3V3 |
- led1 is connected to VCC
Jumper settings
For 2.0
SV2: 3V3 supply selection
1-2: Direct from FPGA board (through 40-pin connector)
2-3: From regulator (see SV3 settings)
SV3: Regulator power source selection
1-2: Powered from USB
2-3: Powered from FPGA board (through 40-pin connector)
For 2.1
J1: 3V3 supply selection
1-2: Direct from FPGA board (through 40-pin connector)
2-3: From regulator (see SV3 settings)
J2: Regulator power source selection
(physical position is the same as in 2.0, only numbering has changed)
1-2: Powered from FPGA board (through 40-pin connector)
2-3: Powered from USB
future hardware enhancements
Changelog
2.1
- Renamed SV2 to J1
- Renamed SV3 to J2
- Jumper settings marked on PCB
- Moved center of mounting holes to 3mm from PCB edge
2.0
- Initial public release